Raj Thummar

Design verification

How a chip bug gets caught.

Design verification means testing a chip’s design on a computer before it is built, to find and fix mistakes early. Once a chip is made, it can never be changed. Two small examples first, then the real blocks from past roles.

  1. Ask
  2. Run
  3. Check
  4. Report
Sanity test

 

The test
2 + 3 = ?
written by hand
Chip design
adder
running in simulationfixed
Expected answer
–
reference model
Checker
–
do they match?
Results log
    2 + 3

    From past roles

    Simplified block diagrams of what was verified.

    TenstorrentSecure boot ROM
    ROM startson power-up Find the flashmain or backup Authenticategenuine image? Decryptunlock payload Start PLL, runhand over control What the tests try to break Main flash missing or baduse backup Signature does not matchrefuse to boot Signing key has been revokedrefuse to boot Older version of the software (anti-rollback)refuse to boot Checked on two different SoCs, then again on the final timing-annotated netlist.
    The boot ROM is the first code a chip runs and cannot be patched later. Verification proves the good path, and every way it should say no.
    AMDLink Level Retry
    Sender Receiver Replay buffercopies kept until acknowledged #1#2#3 #1frame #1 #2frame #2, damaged #3frame #3 (receiver holds it) NACK: resend from #2 replay #2, then #3, from the buffer ACK: buffer slots freed slots free again TimeoutIf NACK or ACKis lost, a timerruns out and thesender replaysanyway.
    If a frame is damaged, the link partner resends it from a buffer. There is no slow end-to-end retransmission.
    Rockport Networks, now CerioReorder Manager
    Sendersends 1, 2, 3 long pathshort pathmedium path with a detour Reorder managerholds early ones output 1 2 3 1 2 3 arrive 2, 3, 1leave 1, 2, 3
    Paths differ in length, so packets arrive out of order. The block under test restores the order, and the scoreboard checks it.